Memory Static “Cache”

Cache memory is designed for memory speed
near the speed of processors in the structure of the cache memory is a direct access from the CPU

Reading Cache Operation

Cache Characteristics:
Mapping techniques
Direct (direct)
Associative (no intermediaries)
Set Assotiative (combined)

Cache Size
Between 64 Kb - 8 MB
Optimum, depending on the generation of computers and processors.

Algorithms process the data replacement:
Recentlyt Least Used (LRU)
First - in - first - out (FIFO)
Least Frequency Used (LFU)
Random

Data Block Size
Optimum up to 8 units of address data



Dynamic RAM is made based on the dynamic semiconductor memory architecture which is based on cells that store data (electric charge) on the capacitor,
presence and absence of the charge represents the data in the form of binary 1 or 0 because the capacitor is naturally experienced discharge cargo,
dynamic RAM requires periodic charging to maintain the charge is known as the refresh frequency in every micro-second.
Some dynamic RAM technology:

CHIP AND RAM (SIMM) → 1 side which utilized
EDO RAM
SDRAM
FPM DRAM
And RDRAM DDRAM


DIMM → 2 side / double side
be used
→ DIMM Dual in-line memory
module